Video decoder with down conversion function and method for decoding video signal

ABSTRACT

The present invention relates to a video decoder with a down conversion function, and a method for decoding a video signal. According to the video decoder and the method for decoding a video signal of the present invention, a VLD analyzes a received compressed video stream, and extracts motion signals. The bitstream analyzed at the VLD is converted into a macro block through an IQ and IDCT in succession, and a MC makes motion compensation of an up sampled data by using the extracted motion signals. A data from the IDCT and a data from the MC are added, down sampled by an adaptive down sampler, and stored in an external memory. For motion compensation, the adaptive up sampler up samples the data down sampled at the adaptive down sampler, and provides to the MC.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a video decoder with a down conversionfunction, and a method for decoding a video signal.

2. Background of the Related Art

In general, an MPEG-2 video decoding chip is provided with a TP(Transport Packet)-decoder, a video decoder, a video display processor,an external memory, and a host interface, and the like. The externalmemory may be a DRAM (Dynamic Random Access Memory) for receiving, andstoring a bitstream, and frame buffers for motion compensation, and thelike. MPEG-2 standard requires a bit buffer size of 10 Mbits forsupporting an MP@HL mode, at a maximum allowable bit rate of 80 Mbits/s.An existing 16 Mbits DRAM basis MPEG-2 decoder requires an externalmemory of approx. 96˜128 Mbits size. Therefore, a price competitivenessis required in view of manufacturers and consumers. For having the pricecompetitiveness, it is required that a good picture quality ismaintained while expensive memory sizes are reduced. However, it isforeseen that an increase of additional external memories is inevitablein the future in light of a trend that various OSD (On Screen Display)and a variety of services are provided.

Recently, in a case of a video compression and decoding system such asMPEG-2, a variety of video signals are multi-decoded and displayed, forproviding a variety of services, when it is required that the variety ofvideo signal are decoded by using a limited capacity of the memory. Atthe end, taking the memory size limitation, price, and a bandwidth of adata bus into account, the video decoding chip is required to beprovided with an effective device for reducing a memory capacity thatcan minimize a loss of a high quality picture signal loss.

In memory reduction algorithms loaded on existing video decoding chips,there are the ADPCM (Adaptive Differential Pulse Coded Modulation) typewith a 50% reduction ratio, and the type with 75% reduction ratio thateliminates spatial duplicity by using VQ (Vector Quantization).

The ADPCM is suggested by Pau and Sano in EP 0778709A1 titled “MPEG-2decoding with a reduced RAM requisite by ADPCM recompression beforestoring MPEG decompressed data”. The VQ is suggested by Bruni et al. inIEEE Trans., On Customer Electronics, pp. 537-544, 1988, titled “A noveladaptive vector quantization method for memory reduction in MPEG-2 HDTVdecoders”.

Compression methods by filtering in a DCT (Discrete CosineTransformation) frequency domain, or down sampling are suggested byS.-B. Ng (“Lower resolution HDTV receivers”, U.S. Pat. No. 5,362,854,Nov. 16, 1993), S.-J. Choi et al. (“Frame memory reduction forMPEG-2/DTV video coding”, Int. workshop on HDTV '98), and R. Mokry andD. Anastassiou (“Minimul error drift in Frequency scalability formotion-compensated DCT coding”, IEEE Trans. On Circuits and Systems forVideo Tech., Vol. 4, August 1994).

Because a compressed code is stored in the memory, the ADPCM method isdifficult to display a video by using a video display right away, torequire a device for decoding the compressed code, additionally. Sincethe ADPCM method shows very great picture quality loss in a case of 75%reduction, the ADPCM method is not suitable for the video decoding chip.

Different from this, a plurality of HDTV class videos or SD class videosreceived at one chip video decoder can be displayed on one screensimultaneously by using a down conversion algorithm. This method canmaintain a good picture quality to some extent despite of substantialreduction of the memory capacity, and applicable to inexpensive decodersfor low resolution displays. Therefore, a down conversion algorithm thatallows to employ a small capacity memory while a good picture qualitycan be maintained, and a hardware design for the down conversionalgorithm, are required.

A general MPEG encoder encodes either a progressive sequence or aninterlaced sequence. An interlaced sequence picture is encoded in fieldor frame units. The field picture has odd scanning lines and evenscanning lines, and all encoder and decoder are operative in field.Therefore, data blocks each DCT Transformed in a 8×8 unit only has oddfields or even fields, which are called as field DCT coded blocks.

Different from this, a frame picture has odd scanning lines and evenscanning lines, resulting in macro blocks of the frame picture to haveodd fields and even fields. However, macro blocks of the frame picturecan be coded in two methods. According to the first method, each of thefour 8×8 discrete cosine transformed blocks is a DCT coded block inframe units each having odd scanning lines and even scanning lines. Onthe other hand, according to the second method, two macro blocks fromthe four macro blocks are blocks DCT coded in field units only havingodd scanning lines of the macro blocks, and the rest of two macro blocksare blocks DCT coded in field units only having even scanning lines.

All the macro block in the field picture are DCT coded in field units,and motion compensation of which are predicted from a reference field inmaking motion compensation. On the other hand, macro blocks in the framepicture are DCT coded in frame units or in field units. Each of themacro blocks in the frame picture is motion compensation predicted inframe units or field units. On the other hand, in a case of theprogressive sequence, all pictures are DCT coded, and motioncompensation predicted in frame units.

Currently, in this state spread of HD displays are not enough, there aremany cases when an HD class picture quality video sequence is displayedin a lower resolution though TV receivers of present NTSC (NationalTelevision System Committee) standards. Therefore, it is required thatusers can watch an HDTV broadcasting signal through the NTSC TVreceivers without buying expensive HDTV (High Definition Television),immediately. As explained, a device for converting the HDTV broadcastingsignal suitable to the NTSC TV receiver is called as a down convertingdecoder. At the end, by employing the down converting decoder, a TVreceiver having a price significantly lower than a TV receiver having aperfect HD class resolution can be obtained.

One of these types is disclosed in U.S. Pat. No. 5,262,854. This patentincludes a down sampler for removing 48 high frequency DCT coefficientsin an 8×8 block. According to this patent, a result of IDCT for the restlow frequency 4×4 blocks is stored in a memory. Therefore, for making anaccurate motion compensation, when it is intended to reduce an error ofmotion compensation prediction by using perfect resolution motionvectors, a frame of reduced resolution is used as reference. At the end,in order to provide a picture of a perfect resolution from a picture ofa reduced resolution, an up-sampling is employed.

A few effective methods are suggested for reducing the error of motioncompensation prediction by up sampling a picture down sampled by using4×4 IDCT, by R. Monky and D. Anastsssiou (“Minimul error drift infrequency scalability for motion-compensated DCT coding”, IEEE Trans. Oncircuits and systems for video Tech., Vol. 4, No.4, August 1994), andJohnson and Princen (“Drift minimization in frequency scaleable codersusing block based filtering”, IEEE workshop on visual signal processingand communication, September 1993. These methods employ two dimensionalfilters each having 5 taps or 8 taps depending on a typically predictedmotion vector of a macro block, when positions of 8 tap filter valuesare changed depending on the motion vector, to require to increase 4pels into 8 pels by one 8 tap filter.

However, while the foregoing methods are suitable to a progressivesequence having DCT coded blocks in frame units, matters on a video ofblocks DCT coded in frame units and DCT coded in field units mixedtherein are not taken into account. Moreover, the foregoing methods havea frame type memory structure, a down converting of blocks DCT coded infield units is carried out after the blocks DCT coded in field units isconverted into blocks DCT coded in frame units, that results inunfavorable influence of prediction error accumulation in making motioncompensation in an area having a great motion. Furthermore, the onlyemployment of low frequency parts (in general, called as 4×4 cuts) among8×8 DCT coefficients in the motion compensation causes to lost signalsof high frequency band, that causes to occur block artifacts.

Eventually, an interlaced sequence processed at an MPEG-2 video decoderhas a problem of data loss occurred in the down conversion.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a video decoder with adown conversion function, and a method for decoding a video signal thatsubstantially obviates one or more of the problems due to limitationsand disadvantages of the related art.

An object of the present invention is to provide a video decoder with adown conversion function, and a method for decoding a video signal whichpermits an SD class display of a small memory capacity to display an HDclass signal.

Another object of the present invention is to provide a video decoderwith a down conversion function, and a method for decoding a videosignal which permits to reduce different video signals in ½, or ¾reduction ratio, and store in an external memory at a time, or displayon one screen at a time, regardless of a progressive scanning typepicture or interlaced scanning type picture.

Additional features and advantages of the invention will be set forth inthe description which follows, and in part will be apparent from thedescription, or may be learned by practice of the invention. Theobjectives and other advantages of the invention will be realized andattained by the structure particularly pointed out in the writtendescription and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purposeof the present invention, as embodied and broadly described, andaccording to a first characteristic of the present invention, frame DCTcoded blocks and field DCT coded block received at the video decoder arealways down converted into a picture of a field basis vertical pelstructure.

According to a second characteristic of the present invention, a macroblock adder module adds a motion compensated macro block from a motioncompensation buffer and an IDCT macro block from a DCT buffer accordingto a picture structure and a DCT type. In a 75% reduction mode, a deviceis included for arranging positions of pels of a block predicted as afield structure to suit to an IDCT type.

According to a third characteristic of the present invention, a downsampler module has modes for horizontal ½ reduction in 8×8 block units,and for vertical and horizontal ¾ reductions.

According to a four characteristic of the present invention, a downsampler module divides a frame DCT coded block into field signals andextracts frequency components in a 8×8 block in a ¾ reduction mode. Inthis instance, different down sampling filters are used in a verticaldown sampling depending on a color component, because a number of fieldsfor chrominance components are smaller than a number of fields forluminance components.

According to a fifth characteristic of the present invention, in a downsampling, down sampled pels are obtained by a down sampling matrixconversion. That is, C_(4×8)=C₄ ^(T)·T₈, where${{C4} = \frac{\begin{bmatrix}T_{4} \\\phi\end{bmatrix}}{\sqrt{2}}},$and T₄ denotes a 4×4 DCT basis matrix, except that C_(2×4)=C₂ ^(T)·T₄filter is used in vertical down sampling of a chrominance component.

According to a sixth characteristic of the present invention, in motioncompensation, a field fit to a motion vector is selected, and reads areduced field reference signal on a memory. Then, horizontal andvertical direction up sampling are carried out for each fields.

According to a seventh characteristic of the present invention, in fieldprediction compensation, a reference address is provided to a memory byusing a motion vector to read a reference block. Then, horizontal andvertical up sampling is carried out for each filed, a ½ pel predictionis made for the up sampled blocks, to provide motion compensated blocks.Finally, the motion compensated blocks are forwarded to a macro blockadder in field units.

According to an eighth characteristic of the present invention, in frameprediction compensation, a reference address is provided to a memory byusing a motion vector, to read field unit reference blocks. Then,horizontal and vertical up sampling is carried out for each field, and aframe unit reference block is formed of up sampled blocks of each field.Then, a motion compensated block is formed by making ½ pel prediction.Finally, motion compensated frame unit blocks are forwarded to a macroblock adder according to IDCT macro block type.

According to a ninth characteristic of the present invention, an upsampler module has a ½ reduction mode in which a horizontal up samplingin 8×4 block units is made, and a ¾ reduction mode in which vertical andhorizontal up sampling in 4×4 block units are made.

According to a tenth characteristic of the present invention, a motioncompensator uses 2·C_(4×8) ^(T), and 2·C_(2×4) ^(T) filters in upsampling in filtering.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the description serve to explain the principles of theinvention:

In the drawings:

FIG. 1 illustrates a block diagram showing a system of a scaleableMPEG-2 video decoder having a down conversion function in accordancewith a preferred embodiment of the present invention;

FIG. 2 illustrates a block diagram showing a system of a video decoderhaving a down conversion algorithm for memory reduction in accordancewith a preferred embodiment of the present invention;

FIG. 3 illustrates a diagram showing a pel architecture after data inDCT domain is down sampled;

FIG. 4 illustrates a diagram showing a form of data from the IDCT andstored in the DCT buffer;

FIG. 5 illustrates a diagram showing a case when an MC buffer convertsand stores a field unit picture into a frame unit picture;

FIG. 6 illustrates a diagram showing a case when an MC buffer stores afield unit picture as it is;

FIG. 7 illustrates a diagram for explaining operation of a macro blockadder;

FIG. 8 illustrates a block diagram showing a detailed system of the downsampler in FIG. 2;

FIG. 9 illustrates a block diagram for explaining operation of the downsampler in FIG.

FIG. 10 illustrates detailed systems of the up sampler and the motioncompensator in FIG. 2;

FIG. 11 illustrates a detailed system of the up sampler 9 in FIG. 2;

FIG. 12 illustrates a block diagram showing a process for up samplingfield data stored in a field basis external memory by means of frameprediction; and,

FIG. 13 illustrates a diagram for explaining a method for making motioncompensation having ½ pel interpolation of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings. The video decoder with a down conversion function of presentinvention relates to a technology required for displaying interlacedscanning, coded, different video signals of HD class on the same screenon the same time, or displaying an HD class signal on a low resolutionclass display. The video decoder of the present invention can reduce acapacity of an external memory by 50% or 75% compared to an existing HDclass video decoder as required, and is applicable to an MPEG-2 (MovingPicture Expert Group-2) decoding chip, a standard in a digital videosignal transmission field.

As explained, the MPEG-2 video decoder of the present invention reducesa video, and stores in a memory or displays on a screen, regardless of aprogressive scanning type picture or an interlaced scanning typepicture. FIG. 1 illustrates a block diagram showing a system of ascaleable MPEG-2 video decoder having a down conversion function inaccordance with a preferred embodiment of the present invention. Thedown conversion function of the system in FIG. 1 is for 50% or 75%memory reduction.

Referring to FIG. 1, the scaleable MPEG-2 video decoder having a downconversion function in accordance with a preferred embodiment of thepresent invention includes a buffer 2 for receiving a compressedbitstream 1, a VLD (Variable Length Decoder) 3 for analyzing thecompressed bitstream from the buffer 2, an IQ (Inverse Quantizer) 4 forinverse quantizing the compressed bitstream analyzed at the VLD 3, anIDCT for inverse discrete cosine transform of the bitstream from the IQ4, an MC (Motion Compensator) 6 for making motion compensation of a dataup sampled by motion signals, such as motion vectors, extracted from theVLD 3, an adder 7 for adding a data from the IDCT 5 and a data from theMC 6, an adaptive down sampler 8 for subjecting a data from the adder toadaptive down sampling, and an adaptive up sampler 9 for up sampling thedata down sampled at the adaptive down sampler 8, and providing to theMC 6. The signal from the down sampler 8 is stored in an external videoframe memory 12 through an internal memory bus 10 and the memoryinterface 11. The data stored in the memory 12 is processed to bedisplayable at a video display processor 14 in response to aninstruction signal provided from the external input device 13, anddisplayed on a display 15. In this instance, the MPEG-2 video decodercarries out IDCT in 8×8 block units according to an MPEG-2 video syntax.On the other hand, in a case of an intra-picture (1-picture), the datasubjected to IQ and IDCT at the IQ 4 and IDCT 5 is stored in theexternal memory right away, and, in a case of a predictive picture(P-picture) or a bi-directional picture (B-picture), the data motioncompensated at the MC 6 and the data subjected to IDCT at the IDCT 5 areadded together at the adder 7 and stored in the external memory 12. Asexplained, the video stored in the external memory 12 is displayed afterthe video is passed through the video display processor 14. The presentinvention is characterized in that the adaptive down sampler 8 and theadaptive up sampler 9 are provided additionally, for storing differentvideo signals, reducing a capacity of the external memory 12, andreducing a bandwidth of the data to be stored in the external memory 12.Both of the adaptive down sampler 8 and the adaptive up sampler 9 reducea size of a video data to be stored in the external memory 12 by ½ or ¼.Also, the two samplers 8 and 9 reduce a drift error occurred duringdecoding of the MPEG video data to a maximum and helps to maintain agood display picture quality.

FIG. 2 illustrates a block diagram showing a system of a video decoderhaving a down conversion algorithm for memory reduction in accordancewith a preferred embodiment of the present invention.

Referring to FIG. 2, the video decoder having a down conversionalgorithm for memory reduction in accordance with a preferred embodimentof the present invention includes a VLD 3 for receiving and analyzing acompressed bitstream, an IQ for subjecting the compressed bitstreamanalyzed at the VLD 3 to IQ, an IDCT 5 for subjecting a bitstream fromthe IQ 4 to inverse discrete cosine transform in 8×8 block units, an MC6 for making motion compensation of an up sampled data by using motionsignals extracted by analysis of the VLD 3, i.e., motion vectors, motiontype, and a motion vertical field selection signal, a DCT buffer 16 forforwarding a data from the IDCT 5 with the data sorted into a top fielddata and a bottom field data by using signals extracted at the VLD 3,i.e., a DCT type, a picture architecture, and a progressive sequencesignal, an MC buffer 17 for forwarding a data from the motioncompensator 6 with the data sorted into a top field data and a bottomfield data by using the DCT type, the picture architecture, and theprogressive sequence signal, an adder 18 for adding the top field datafrom the DCT buffer 16 and the top field data from the MC buffer 17, anadder 19 for adding the bottom field data from the DCT buffer 16 and thebottom field data from the MC buffer 17, an adaptive down sampler 8 forsubjecting the top field data and the bottom field data from the twoadders 18 and 19 to adaptive down sampling, an external memory 12 forstoring the down sampled data, i.e., a reduced resolution data and amotion compensated data, and an adaptive up sampler 9 for up samplingthe down sampled data stored in the external memory 12 and forwarding tothe MC 6.

In general, the MPEG-2 video decoder reads pels in frame units or fieldunits from the external memory 12 according to architecture framepicture or field picture, and makes motion compensation. However, in thevertical direction down sampling for 75% memory capacity reduction,results of down sampling differ for the frame picture and the fieldpicture. FIG. 3 illustrates a diagram showing a pel architecture afterdata in DCT domain is down sampled.

Referring to FIG. 3, when a block DCT coded in frame units, and a blockDCT coded in field units are down sampled in a DCT transform domainrespectively, results thereof show pel architecture different from theother, and, particularly, information on a field kind is lost when amotion compensation is made, or the video data in the interlacedscanning type is displayed in field units. In order to compensate forthis, the present invention suggests to store the DCT blocks in theexternal memory 12 in a vertical pel architecture based on a field fixedalready regardless of one DCT block in a received video sequence is ablock DCT coded in field units or a block DCT coded in frame units.Thereafter, a compensation for a motion prediction is made. Therefore,even if a frame picture is down sampled in a vertical direction,information on a field kind is not lost, and, furthermore, a goodpicture quality can be maintained.

The operation of the video decoder in FIG. 2 will be explained.

The DCT coefficients analyzed at the VLD 3 is provided to the IDCT (or amodule) 5 after the DCT coefficients are passed through an inversequantizing process through the IQ 4, when the VLD 3 also provides asignal indicating that the received video signal has a DCT type frame orfield, and a signal indicating the received video signal is a framepicture of a picture architecture or a field picture. The VLD 3 alsoprovides the motion vectors MV, a motion type signal motion_type, and amotion vertical field selection signals motion_vertical_field_select. Inthe meantime, the two adders 18 and 19 in the macro block adder MB_ADD 7in FIG. 1 add outputs both of the DCT buffer 16 and the MC_buffer 17 tosuit to forms of data from the IDCT 5, respectively. Then, data from theadders 18 and 19 are down sampled at the adaptive down sampler 8.

FIG. 4 illustrates a diagram showing a form of data from the IDCT andstored in the DCT buffer. In a case of an interlaced scanning type framepicture, in a DCT type code dc_cal_type, there are a frame typedct_type=‘0’ and a field type dct_type=‘1’. When a DCT calculation typecode dc_cal_type representing a frame architecture in 8×8 block units isset to be “1”, shuffling of data in field units is carried out. In FIG.4, code progressive_seq=‘1’ represents a progressive scanning sequence,code progressive_seq=‘0’ represents an interlaced scanning sequence,code picture_structure=‘01’ represents a top field, codepicture_structure=‘10’ represents a bottom field, codepicture_structure=‘11’ represents a frame picture, code dct_type=‘0’represents a frame DCT, code dct_type=‘1’ represents a field DCT, andcode dc_cal_type=‘0’ represent existence of no data.

FIG. 5 illustrates a diagram showing a case when an MC buffer convertsand stores a field unit picture into a frame unit picture, and FIG. 6illustrates a diagram showing a case when an MC buffer stores a fieldunit picture as it is.

Referring to FIGS. 5 and 6, the MC buffer receives, and stores a pictureeither in a frame structure or in a field structure depending on apicture structure. As explained, the video decoder of the presentinvention stores a picture data based on the field structure. Therefore,when the video decoder forms a macro block for a motion compensation,the video decoder accesses to the external memory 12 and reads pelvalues therein in field units. Therefore, in general, in motioncompensation for a field picture, the MC_buffer 17 is formed in fieldunits as shown in FIG. 6. However, in frame picture motion compensationtypes, there are frame unit motion compensation MC-FRAME, and field unitmotion compensation MC_FIELD, MC_DMV. At the end, as shown in FIG. 5, inorder to obtain a frame structure macro block, pels from the fieldstructure macro block is required to be converted into a frame structuremacro block. Finally, a form of the pels stored in the MC_buffer 17 ismade suitable to the picture structure provided to the video decoder.

FIG. 7 illustrates a diagram for explaining operation of a macro blockadder.

Referring to FIG. 7, the macro block adder 7 adds data from theMC_buffer 17 and the DCT_buffer 16 such that pels at the same positionsare added according to the DCT type and the picture structure.

FIG. 8 illustrates a block diagram showing a detailed system of the downsampler 8 in FIG. 2.

Referring to FIG. 8, the down sampler 8 includes a down samplingcontrolling part 20 for controlling down sampling according to receiveddown sampling parameters, a vertical down sampling part for downsampling a received data in a vertical direction under the control ofthe down sampling controlling part 20, a temporary buffer 22 fortemporary storage of the vertical down sampled data, a horizontal downsampling part 23 for down sampling data from the temporary buffer 22 ina horizontal direction under the control of the down samplingcontrolling part 20, and a forwarding multiplexer 24 for forwardingeither of the received data and a data from the horizontal down samplingpart 23 selectively under the control of the down sampling controllingpart 21. The down sampler 8 reduces sizes of original data according to1, ½, and ¾ reduction ratios for respective field signals from the macroblock adders MB_ADD 18 and 19. To do this, the down sampler 8 includesseparate processors for the vertical direction and the horizontaldirection. In the ½ original data reduction, the down sampler 8 makes ahorizontal down sampling only.

The following is a down sampling equation. $\begin{matrix}{{\lbrack X\rbrack = {\begin{bmatrix}X_{0} \\X_{1} \\X_{2} \\X_{3} \\X_{4} \\X_{5} \\X_{6} \\X_{7}\end{bmatrix} = {T_{S}\lbrack x\rbrack}}},} & (1)\end{matrix}$

-   -   where, [X] denotes 8 DCT coefficients, and [x] denotes 8 pel        values. $\begin{matrix}        {{\lbrack{T8}\rbrack = \begin{bmatrix}        t_{00} & t_{01} & t_{02} & t_{03} & t_{04} & t_{05} & t_{06} & t_{07} \\        t_{10} & t_{11} & t_{12} & t_{13} & t_{14} & t_{15} & t_{16} & t_{17} \\        t_{20} & t_{21} & t_{22} & t_{23} & t_{24} & t_{25} & t_{26} & t_{27} \\        t_{30} & t_{31} & t_{32} & t_{33} & t_{34} & t_{35} & t_{36} & t_{37} \\        t_{40} & t_{41} & t_{42} & t_{43} & t_{44} & t_{45} & t_{46} & t_{47} \\        t_{50} & t_{51} & t_{52} & t_{53} & t_{54} & t_{55} & t_{56} & t_{57} \\        t_{60} & t_{61} & t_{62} & t_{63} & t_{64} & t_{65} & t_{66} & t_{67} \\        t_{70} & t_{71} & t_{72} & t_{73} & t_{74} & t_{75} & t_{76} & t_{77}        \end{bmatrix}},} & (2)        \end{matrix}$    -   where, [T8] represents an 8×8 DCT matrix of 8-point DCT bases.

Similar to equation (2), a 4×4 DCT matrix of 4-point DCT bases isrepresented with [T4]. A down sampling process of removing highfrequency components in the horizontal direction and in the verticaldirection, and subjecting to IDCT can be expressed with the followingequation. $\begin{matrix}{{\begin{bmatrix}y \\y \\y \\y \\0 \\0 \\0 \\0\end{bmatrix} = {\left\lbrack {P4}^{T} \right\rbrack\begin{bmatrix}X_{0} \\X_{1} \\X_{2} \\X_{3} \\X_{4} \\X_{5} \\X_{6} \\X_{7}\end{bmatrix}}},} & (3)\end{matrix}$

-   -   where, [P4] represents $\begin{matrix}        {\lbrack{P4}\rbrack = {\frac{\begin{bmatrix}        {T4} & \phi \\        \phi & \phi        \end{bmatrix}}{\sqrt{2}}.}} & (4)        \end{matrix}$

At the end, an one dimensional down sampling can be expressed as thefollowing equation (5) by using equations (2) and (3). $\begin{matrix}{{y_{4 \times 1} = {{C_{4}^{T} \cdot X_{8 \times 1}} = {\frac{\left\lbrack {T_{4}^{T}\phi} \right\rbrack}{\sqrt{2}} \cdot \lbrack{T8}\rbrack \cdot X_{8 \times 1}}}},} & (5)\end{matrix}$where, ‘x’represents 8×1 pels, ‘y’ represents down sampled 4×1 pels, and‘X’ represents coefficient blocks subjected to DCT with respect to ‘x’.And, $C_{4} = {\frac{\begin{bmatrix}T_{4} \\\phi\end{bmatrix}}{\sqrt{2}}.}$Then, the equation (5) can be expressed in the following equation (6).y _(4×1) =C _(4×8) ·X _(8×1)  (6),where, C_(4×8)=C₄ ^(T)·T₈ is defined as a 4×8 dimension down samplingmatrix, which converts 8 pels into 4 pels.

Similar to the equation (6), a down sampling matrix having an input of 4pels and an output of 2 pels can be represented as the followingequation (7).Y _(2×1) =C _(2×4) ·X _(4×1)  (7),where, C_(2×4) represents ${\begin{bmatrix}T_{2} \\\phi\end{bmatrix}^{T} \cdot \frac{T_{4}}{\sqrt{2}}},$and T₂ represents a matrix based on 2×2 DCT as shown in the equation(2).

FIG. 9 illustrates a block diagram for explaining operation of the downsampler in FIG. 2, showing a field basis down sampling by using theequations (6) and (7).

Referring to FIG. 9, in a 50% original data reduction, only a horizontaldown sampling is carried out, when an 8×8 field block is converted intoan 8×4 field block by using the matrix in the equation (6), and storedin the external memory 12. In 75% original data reduction, it isrequired to process a luminance signal ‘Y’ and a chrominance signal ‘C’in the original data separately for maintaining information on field inthe external memory 12. As shown in FIG. 4, in a case of framestructured picture, the chrominance signal “C” is divided into a 4×8sized top field and a 4×8 sized bottom field. Different from thechrominance signal, the luminance signal ‘Y’ is divided into an 8×8sized top field and an 8×8 sized bottom field. At the end, since thechrominance signal has a number of vertical direction field lines halfof the luminance signal, down conversion is carried out, by using theequation (7) for the chrominance signal, and by using the equation (6)for the luminance signal. Finally, as shown in FIG. 3, the downconverted field unit pels are stored in the external memory 12.

FIG. 10 illustrates detailed systems of the up sampler and the motioncompensator in FIG. 2, showing a motion compensation for an up sampling.

Referring to FIG. 10, the motion compensator having up samplers includesa motion vector translator 28 for translating a motion type signal, amotion vector, and a motion vertical field selection signal from the VLD3, to obtain a reference memory read address, and a reference pel forprediction, a horizontal up sampling filter 29 for making a horizontalup sampling by using the motion vector, the reference memory address,and the reference pels for prediction, a vertical up sampling filter 27for making a vertical up sampling a data from the horizontal up samplingfilter 29 by using the motion vector, and the motion type, a combiner 26for combining up sampled field blocks from the vertical up samplingfilter 27 into frame blocks when a frame prediction is used, and an ½pel interpolator 25 for interpolating a data from the combiner 26 by ½pels, and forwarding to the MC_buffer 17.

The operation of the video decoder for the foregoing motion compensationwill be explained.

In a case of an intra picture, a result passed through the IDCT 5 inFIG. 2 is down sampled right away, and stored in the external memory 12.On the other hand, a prediction picture ‘P’ or a bi-directional picture‘B’ is added to motion prediction compensated blocks, and stored in theexternal memory 12. On the other hand, in order to obtain a motioncompensated frame, a video encoder in a transmission side reproduces thepresent frame block from a prior frame by using a motion vector MV of aperfect resolution. Therefore, for enhancing a picture quality, thepresent invention uses the motion vector of a perfect resolution as itis, rather than scaling down the vertical and horizontal motion vectors.At first, for using the motion vector MV of a perfect resolution, it isrequired to up sample a reference picture of a reduced resolution storedin the external memory 12 to a picture of an original resolution.

As explained, the external memory 12 in FIG. 2 has field based verticalstructure pictures stored therein. In the MPEG video, there are a frameprediction and field prediction according to motion types. In the fieldprediction, an up sampling is made for fields selected in response to amotion vertical field selection signal motion_vertical_field_select.However, in a case of the frame prediction, after the top field and thebottom field are up sampled respectively, one frame block is providedfrom two up sampled fields. Then, a frame predicted block is providedand ½ pel prediction is carried out.

In this instance, a picture quality is greatly dependent oncharacteristics of the up sampling filter. The up sampling filter typeused in the present invention, a reverse type of the foregoing downsampling type, uses a matrix of the DCT bases. FIG. 11 illustrates adetailed system of the up sampler 9 in FIG. 2.

Referring to FIG. 11, the up sampler 9 includes an up samplingcontrolling part 30 for controlling up sampling according to received upsampling parameters, a horizontal up sampling part 31 for subjecting areceived data to horizontal up sampling under the control of the upsampling controlling part 30, a temporary buffer 32 for temporarystorage of the horizontal up sampled data, a vertical up sampling part33 for subjecting a data from the temporary buffer 32 to vertical upsampling under the control of the up sampling controlling part 30, and aforwarding multiplexer 34 for forwarding either the received data or adata from the vertical up sampling part 33 under the control of the upsampling controlling part 31, selectively. As shown in FIG. 11, alikethe down sampler, the up sampler adjusts extents of vertical andhorizontal up sampling according to unity, ½, or ¾ reduction mode. Foran example, in the ½ reduction mode, only horizontal up sampling ismade, and in the ¾ reduction mode, both vertical and horizontal upsampling are made.

Above up sampling, reversal of the equation (6), converts four pels into8 pels by using the following equations. At first, upon obtaining DCTcoefficients for four pels, and making all DCT coefficients to be ‘0’for the rest of high frequencies, the following equation is obtained.$\begin{matrix}{X_{\lbrack{8 \times 1}\rbrack}^{1} = {{\begin{bmatrix}{T4} \\\phi\end{bmatrix} \cdot \sqrt{2} \cdot y_{4 \times 1}} = {C_{4} \cdot y_{4 \times 1} \cdot 2}}} & (8)\end{matrix}$

A result of conduction of an 8-point IDCT according to the equation (8)can be expressed in the following equation (9).X _([8×1]) ^(UP) T8^(T) ·X _([8×1]) ¹  (9)

At the end, equations (8) and (9) can be expressed as the followingequation (10).X _([8×1]) ^(UP) =T8^(T) ·C ₄ ·y _(4×1)·2=2·C _(4×8) ^(T) ·y_(4×1)  (10)

Above equation (10) represents a process for up sampling a picture witha ½ resolution stored in the memory 2. A process for up sampling fromthe down sampled pel explained in the equation (7) to four pels can beexpressed in the following equation (11).X _([4×1]) ^(UP) =T4^(T) ·C ₂ ·y _(2×1)·2=2·C _(2×4) ^(T) ·y_(2×1)  (11)

FIG. 12 illustrates a block diagram showing a process for up samplingfield data stored in a field basis external memory by means of frameprediction.

Referring to FIG. 12, a luminance signal and a chrominance signal are upsampled, separately. At first, up sampling of the luminance signal willbe explained. A data from the field structure memory 12 is up samplingfiltered by using the up sampling matrix, to obtain an up sampled topfield and bottom field, which are added together. The added data is ½pel predicted, and forwarded to the macro block adder 7 in FIG. 2. Next,up sampling of a chrominance signal will be explained. A data from thefield structure memory 12 is up sampling filtered by using the upsampling matrix in the equation (11), to obtain an up sampled top fieldand bottom field respectively, which are added together. The added datais ½ pel predicted and forwarded to the macro block adder 7 in FIG. 2.In other words, the data from the field structure memory 12 isreproduced into a macro block in conformity to original resolution invertical and horizontal directions, and a motion compensation block isobtained from this reproduced block. Alike the down sampling, thevertical up sampling of the chrominance signal is carried out by usingthe matrix in the equation (11). Particularly, in the case of 75% memoryreduction, if a ½ pel interpolation presents in vertical and horizontaldirections, or a motion vector MV of a perfect resolution is not anexact multiple of 8, adjacent 4×4 unit blocks in vertical and horizontaldirections are taken for motion compensation.

FIG. 13 illustrates a diagram for explaining a method for making motioncompensation having ½ pel interpolation of the present invention.

Referring to FIG. 13, in order to produce a macro block D0 of anoriginal picture from a memory of a reduced resolution, blocks B1, B2,B3, and B4 adjoining to a macro block B0 of a reduced resolution aretaken. Then, blocks D1, D2, D3, and D4 of perfect resolutions invertical and horizontal directions are restored from the blocks B1, B2,B3, and B4 by using the up sampling matrices derived in the equations(10) and (11). A ½ pel interpolation is carried out for area D0 of amotion vector MV of perfect resolution, to obtain a desired motioncompensated block. When a 50% memory reduction is desired, if no ½ pelinterpolation is present in a horizontal direction, or a horizontalmotion vector MV of a perfect resolution is not an exact multiple of 8,adjoining blocks in a horizontal direction are taken, and up sampled byusing the equation (10), and a ½ pel interpolation is carried out.

Blocks motion compensated according to the foregoing process is downsampled at the down sampler, and stored in the external memory 12,again. Then, the stored data is displayed on a display through the videodisplay processor.

As has been explained, the video decoder with a down conversionfunction, and the method for decoding a video signal have the followingadvantages. First, the scaleable video decoder of an HD class MPEGsequence of the present invention can reduce memory capacity by 50% or75% effectively while a picture quality is maintained.

Second, the implementation of a video decoder for PIP (Picture InPicture) or low resolution display is very easy.

Third, a plurality of HD class video signals and a plurality of SD classvideo signals can be displayed on one screen by employing a memory of acapacity for processing one HD class video signal only.

Fourth, an HD class video signal can be displayed on a display of a lowresolution without any additional expense for hardware.

Fifth, as an essential source technology in application fields ofdigital TV broadcasting and video conference, implementation of a highperformance video that can make multi-decoding or process a plurality ofpictures is possible.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the video decoder with adown conversion function, and a method for decoding a video signal ofthe present invention without departing from the spirit or scope of theinvention. Thus, it is intended that the present invention cover themodifications and variations of this invention provided they come withinthe scope of the appended claims and their equivalents.

1. A video decoder comprising: a VLD (Variable Length Decoder) foranalyzing a received compressed bitstream; an IQ (Inverse Quantizer) forinverse quantizing the compressed bitstream analyzed at the VLD; an IDCTfor discrete cosine transform of a data from the IQ; an MC (MotionCompensator) for making motion compensation of a data up sampled byusing motion signals extracted at the VLD; an adder for adding a datafrom the IDCT and a data from the MC; an adaptive down sampler of amatrix for converting a data from the adder to be in conformity with apicture structure of the compressed bitstream, subjecting the data toadaptive down sampling, and storing the data in an external memory in afield basis; and, an adaptive up sampler of a structure converted into atransposed matrix of a matrix form for up sampling the data down sampledat the adaptive down sampler, and providing to the MC.
 2. A videodecoder as claimed in claim 1, wherein the compressed bitstream is anMPEG-2 signal.
 3. A video decoder as claimed in claim 2, wherein theMPEG-2 signal is a predictive picture signal or a bi-directional picturesignal.
 4. A video decoder as claimed in claim 1, wherein the videodecoder carries out IDCT in 8×8 block units to suit to a MPEG-2 videosyntax.
 5. A video decoder comprising: a VLD for analyzing a receivedcompressed bitstream; an IQ for inverse quantizing the bitstreamanalyzed at the VLD; an IDCT for inverse discrete cosine transform of adata from the IQ in macro block units; an MC for making motioncompensation of a data up sampled by using motion vectors, a motiontype, and a motion vertical field selection signal extracted at the VLD;a DCT buffer for separating a data from the IDCT into a top field dataand a bottom field data by using a DCT type signal, a picture structuresignal, and a progressive sequence signal extracted at the VLD; an MCbuffer for separating a data from the MC into a top field data and abottom field data by using the DCT type signal, the picture structuresignal, and the progressive sequence signal; a first adder for addingthe top field data from the DCT buffer and the top field data from theMC; a second adder for adding the bottom field data from the DCT bufferand the bottom field data from the MC; an adaptive down sampler forsubjecting added top field data and added bottom field data from abovetwo adders to adaptive down sampling, and storing in an external memory;and, an adaptive up sampler for up sampling a down sampled data storedin the external memory and providing to the MC.
 6. A video decoder asclaimed in claim 5, wherein the block is an 8×8 block.
 7. A videodecoder as claimed in claim 5, wherein the down sampler includes; a downsampling controlling part for controlling down sampling according toreceived down sampling parameters, a vertical down sampling part fordown sampling a received data in a vertical direction on a data from theadders under the control of the down sampling controlling part, atemporary buffer for temporary storage of the vertical down sampleddata, a horizontal down sampling part for down sampling a data from thetemporary buffer in a horizontal direction under the control of the downsampling controlling part, and a forwarding multiplexer for forwardingeither of the received data and a data from the horizontal down samplingpart selectively under the control of the down sampling controllingpart.
 8. A video decoder as claimed in claim 7, wherein the down samplerreduces each field data from the adders by one of reduction ratiosselected from unity, ½, and ¾.
 9. A video decoder as claimed in claim 8,wherein the down sampler carries out down sampling only in a horizontaldirection when the down sampler reduces an original data by the ½reduction ratio.
 10. A video decoder as claimed in claim 5, wherein themotion compensator and the up sampler includes; a motion vectortranslator for translating a motion type signal, a motion vector, and amotion vertical field selection signal from the VLD, to obtain areference memory read address, and a reference pel for prediction, ahorizontal up sampling filter for making a horizontal up sampling byusing the motion vector, the reference memory address, and the referencepels for prediction, a vertical up sampling filter for making a verticalup sampling a data from the horizontal up sampling filter by using themotion vector, and the motion type, a combiner for combining up sampledfield blocks from the vertical up sampling filter into up sampled frameblocks when a frame prediction is used, and an ½ pel interpolator forinterpolating a data from the combiner by ½ pels, and forwarding to theMC_buffer.
 11. A video decoder as claimed in claim 5, wherein, when thereceived bitstream is an intra picture, data from the IDCT is stored inthe external memory right away after the data is down sampled.
 12. Avideo decoder as claimed in claim 5, wherein the up sampler includes; anup sampling controlling part for controlling up sampling according toreceived up sampling parameters, a horizontal up sampling part forsubjecting a data accessed from the external memory to horizontal upsampling under the control of the up sampling controlling part, atemporary buffer for temporary storage of the horizontal up sampleddata, a vertical up sampling part for subjecting a data from thetemporary buffer to vertical up sampling under the control of the upsampling controlling part, and a forwarding multiplexer for forwardingeither the data access by the external memory or a data from thevertical up sampling part under the control of the up samplingcontrolling part, selectively.
 13. A video decoder as claimed in claim12, wherein the up sampler adjusts extents of up sampling in horizontaland vertical directions according to unity, ½, or ¾ reduction mode. 14.A video decoder as claimed in claim 13, wherein the up sampler carriesout up sampling only in a horizontal direction in the ½ reduction mode,and in vertical and horizontal directions in the ¾ reduction mode.
 15. Avideo decoder as claimed in claim 13, wherein, when C_(4×8) ^(T) denotesa 4×8 dimension down sampling transposed matrix, and y_(4×1) denotes adown sampling pel value, the up sampler of a luminance carries out upsampling by carrying out 2·C_(4×8) ^(T)·y_(4×1), and, when y_(2×1)denotes a down sampled 2×1 pels, and C_(2×4) denotes a down samplingmatrix of 2×4 dimension, the up sampler of chrominance carries out upsampling by carrying out X_([4×1]) ^(UP)2·C_(2×4)·y_(2×1).
 16. A methodfor decoding a video signal, comprising the steps of: (a) detectingsignals related to a motion and a picture structure signal from areceived video sequence; (b) processing the received video sequence, forproviding data of macro block units; (c) subjecting the data of macroblock units to down conversion, and storing in an external memory as afield basis vertical pel structure; and, (d) subjecting the downconverted data stored in the external memory to motion predictioncompensation by using the detected motion signals, and the picturestructure signal, to obtain a final down converted data.
 17. A method asclaimed in claim 16, wherein the step (b) includes the steps of,subjecting the video sequence to VLD to obtain DCT coefficients,subjecting the DCT coefficients to inverse quantizing, and subjectinginverse quantized coefficients to IDCT, to provide data of the macroblock unit.
 18. A method as claimed in claim 16, wherein the macro blockunit is 8×8 block suitable for MPEG-2.
 19. A method as claimed in claim16, wherein the detected motion related signals includes a motion vectorsignal, a motion type signal, and a motion vertical field selectionsignal.
 20. A method as claimed in claim 16, wherein the step (d)includes the steps of, making access to pel values in field units fromthe external memory for the motion compensation, converting the accessedfield unit pel values if the detected picture structure signal is aframe picture, and making motion prediction compensation on the frameunit pel values.
 21. A method as claimed in claim 16, wherein the step(d) includes the steps of, dividing the frame picture signal into aluminance signal and a chrominance signal, subjecting a luminance dataaccessed from the external memory to up sampling filtering by using anup sampling matrix of 2·C_(4×8) ^(T)·y_(4×1) (C_(4×8) ^(T) denotes a 4×8dimension down sampling transposed matrix, and y_(4×1) denotes a downsampled pel value), to obtain up sampled top field and bottom field,respectively, adding the top field and bottom field of the up sampledluminance data together, subjecting the added luminance signal data to ½pel prediction, subjecting a chrominance data accessed from the externalmemory to up sampling filtering by using an up sampling matrix ofX_([4×1]) ^(UP)=2·C_(2×4)·y_(2×1) (where C_(2×4) denotes a 2×4 dimensiondown sampling transposed matrix, and y_(2×1) denotes a down sampled pelvalue), to obtain up sampled top field and bottom field, respectively,adding obtained top field and bottom field of the chrominance data, andsubjecting the added chrominance data to ½ pel prediction.
 22. A methodas claimed in claim 21, wherein the step of obtaining top fields andbottom fields of the luminance data and the chrominance data, beforecarrying out up sampling filtering for obtaining ½ pel interpolation,includes the steps of; making access to a macro block of a reducedresolution from the external memory, taking blocks adjoining to themacro block of the reduced resolution for producing a macro block of anoriginal picture, and restoring blocks of perfect resolutions invertical and horizontal directions of the taken adjoining blocks byusing up sampling matrices of X_([×1]) ^(UP)=2·C_(4×8) ^(T)·y_(4×1)(where C_(4×8) ^(T) denotes a 4×8 dimension down sampling transposedmatrix, and y_(4×1) denotes a down sampled pel value), and X_([4×1])^(UP)=2·C_(2×4)·y_(2×1) (where C_(2×4) denotes a 2×4 dimension downsampling transposed matrix, and y_(2×1) denotes a down sampled pelvalue).
 23. A method as claimed in claim 21, wherein the step ofobtaining top fields and bottom fields of the luminance data and thechrominance data, before carrying out up sampling filtering forobtaining ½ pel interpolation, includes the steps of; malting access toa macro block of a reduced resolution from the external memory, takingblocks adjoining to the macro block of the reduced resolution in ahorizontal direction if there is a ½ pel interpolation in the horizontaldirection or a horizontal perfect resolution motion vector is not exactmultiple of 8, and up sampling the taken adjoining blocks by usingX[8×1]^(UP)=2·C_(4×8) ^(T)·y_(4×1) (where C_(2×4) ^(T) denotes a 4×8dimension down sampling transposed matrix, and y_(4×1) denotes a downsampled pel value).
 24. A method as claimed in claim 16, wherein thestep (c) includes, when the picture structure signal is for framepicture and it is intended to reduce the picture by 75%, the steps of;dividing the chrominance signal into n×2n sized top field and bottomfield, and dividing the luminance signal to 2n×2n top field and bottomfield, and down sampling the chrominance signal by using an equationy_([2×1])=C_(2×4)·X_(4×1) (where C_(2×4) denotes a down sampling matrixof 2×4 dimension, and y_(4×1) denotes 4×1 pels), and down sampling theluminance signal by using an equation y_([4×1)]=C_(4×8)·X_(8×1) (whereC_(4×8) denotes a down sampling matrix of 4×8 dimension, and X_(8×1)denotes 8×1 pels).
 25. A method as claimed in claim 24, wherein the n×2ndenotes 4×8, and 2n×2n denotes 8×8.